For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In other instances, silicon-on-insulator substrates are preferred because of the improved short-channel behavior of tri-gate transistors.
Silicon-on-insulator substrates, formed either by global isolation or local isolation, may also be used to fabricate gate-all-around devices. Many different techniques have been attempted to fabricate such three-dimensional isolated channel devices. However, significant improvements are still needed in the area of isolation formation for such semiconductor devices.
In another aspect, many different techniques have been attempted to improve the mobility of transistors. However, significant improvements are still needed in the area of electron and/or hole mobility improvement for semiconductor devices.